High gate leakage current of nitrided silicon dioxide and depletion effect of polysilicon gate electrodes limits the performance of conventional silicon oxide based gate electrodes. High performance devices for an equivalent oxide thickness (EOT) less than 1 nm require high dielectric constant (high-k) gate dielectrics and metal gate electrodes to limit the gate leakage current and provide high on-currents. Since high-k dielectric materials need to be stable in contact with silicon at a temperature high enough to activate electrical dopants, only a handful of materials are known to be practically useful as a high-k gate dielectric. These include ZrO2, HfO2, other dielectric metal oxides, alloys thereof, and their silicate alloys.
A high-k dielectric material needs to provide good electrical stability, that is, the amount of charge trapped in the high-k dielectric material needs to remain at a low level even after extended operation of a transistor. The high-k dielectric material needs to be scalable, that is, to provide an acceptable level of leakage and acceptable levels of electron and hole mobility at a reduced thickness, e.g., less than 1 nm. While the mechanisms for degradation of mobility associated with thin high-k dielectric materials are not fully understood, it is generally believed that trapped charge scattering and/or phonon scattering are primary causes.
In general, complementary metal oxide semiconductor (CMOS) integration requires two gate materials, one having a work function near the valence band edge of the semiconductor material in the channel and the other having a work function near the conduction band edge of the same semiconductor material. In CMOS devices having a silicon channel, a conductive material having a work function of about 4.0 eV is necessary for n-type metal oxide semiconductor field effect transistors (NMOSFETs) and another conductive material having a work function of about 5.0 eV is necessary for p-type metal oxide semiconductor field effect transistors (PMOSFETs). In conventional CMOS devices employing polysilicon gate materials, a heavily p-doped polysilicon gate and a heavily n-doped polysilicon gate are employed to address the needs. In CMOS devices employing high-k gate dielectric materials, suitable materials satisfying the work function requirements are needed. So far, identification of materials for a dual work function metal gate electrode system has presented some challenges.
One approach in implementing high-k dielectrics in CMOS devices is to employ heavily doped polysilicon materials along with high-k gate dielectric materials in the gates. A threshold voltage (Vt) offset is observed, however, when high-k gate dielectric materials are integrated with polysilicon gate electrodes, which can be as much as 600 mV for p-type metal oxide semiconductor (PMOS) devices. The source of the offset is in general believed to be oxygen vacancies, or oxygen deficiencies, as well as Fermi-level pinning due to metal-silicon bonds in the high-k gate dielectrics. While metal gate electrodes tend to mitigate the threshold voltage offset effect, no solution has been proposed to fundamentally address the Vt shift in high-k dielectric gates having a polysilicon gate conductor.
In view of the above, there exists a need for a semiconductor structure having high-k dielectric material gates and providing optimal threshold voltages to PMOSFETs and NMOSFETs, and methods of manufacturing the same.
Particularly, there exists a need for a semiconductor structure having PMOSFETs and NMOSFETs, in which the threshold voltage shift effect in PMOSFETs is eliminated or alleviated, and methods of manufacturing the same.